Not Applicable.
The present invention relates to the field of data communications, and more particularly, to the field of framing data in a communications system.
In data communications, data is generally transmitted in a serial communications format through current networks. It is often the case that the data to be transmitted between two data endpoints is packaged according to specific data communications protocols to facilitate the transmission across the particular network in question. This packaging may include the addition of network management and other information such as headers and trailers to the data to facilitate transmission based upon the dictates of the particular protocol employed. Such packaging is generally termed xe2x80x9cframingxe2x80x9d in the art.
Some of these protocols may include, for example, data transmission using time division multiplexing (TDM) approaches such T1 and E1 standards known in the art. Other example standards may include high-level data link control (HDLC) or asynchronous transfer mode (ATM). Each of these protocols have their own applications and goals in terms of history, performance, error-immunity, flexibility, and other factors. Consequently, each of these protocols employ framing procedures by which data is packaged for transmission across the various networks employed. These protocols are generally incompatible and require translation or conversion to transmit data in a transmission link that employs two or more protocols in two or more different segments.
The conversion from one protocol to another requires specific framing technology to accomplish the task. With a myriad of standards between which conversion is possible, many different dedicated protocol conversion units have been developed to accomplish the specific conversion tasks presented. The typical protocol conversion unit is labeled xe2x80x9cdedicatedxe2x80x9d above because such units generally employ dedicated circuits which are capable only of performing the conversion from one specific protocol to another. The result of this fact is a multitude of protocol conversion units on the market to accomplish the individual conversion tasks, thereby diminishing efficiencies to be obtained by mass production.
It is also the case that new communications standards are developed as data communication technology develops over time. Often times, a particular standard may be in flux while discussion ensues among those skilled in the art until agreement on concrete provisions articulating a standard is reached. Consequently, it is difficult to develop data communications technology that employs an up and coming standard until the standard is settled. In the competitive world of data communications technology production, it is desirable to produce products to meet these new standards as quickly as is possible after a standard is finalized so as to compete in the marketplace.
However, many data communications protocols are not particularly suited for processing as they employ odd numbers of data blocks for various signaling and other functions that with bit sizes that do not match the data bus of conventional programmable processors. As a result, an inordinate amount of processor time is necessary to achieve data protocol conversions in such settings.
In light of the foregoing, it is an objective of the present invention to provide for technology which is programmable to achieve protocol conversions between any number of protocols to obtain the efficiencies of mass production and feature the flexibility allowing the unit to be quickly adapted to new data communications protocols as they develop.
In addition, another objective of the present invention is to provide for a protocol conversion unit which is programmable to convert a first data communications protocol into a second communications protocol that employs a processor with less than full parallel data transfer to facilitate the conversion without requiring an inordinate amount of processor time.
In furtherance of these and other objectives, the present invention entails a system to perform partial byte writes in a processor circuit. The system comprises a bit assembly circuit having a bit assembly register with a corresponding shadow register. Also included is a bit routing circuit configured to transfer at least one data bit from a data bus to a predetermined register position in the bit assembly register with a corresponding shadow bit written to the shadow register. The shadow bit indicates that the data bit written comprises valid data. The bit assembly and shadow registers may receive data directly from the data bus as well.
Using this circuitry, a partial parallel data block is assembled in the bit assembly register. Thereafter, the partial parallel data block is transferred to a destination register via the data bus with corresponding shadow bits being transmitted to the destination shadow register. The valid data is processed accordingly.
In accordance with another aspect of the present invention, a method is provided for performing a partial parallel data transfer which comprises the steps of assembling a partial parallel data block for transfer to a destination register, transferring the partial parallel data block to the destination register, and finally, indicating the validity of a data bit in the partial parallel data block transferred to the destination register.
Other features and advantages of the present invention will become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional features and advantages be included herein within the scope of the present invention, as defined by the claims.